# 1:/timings/default_timings.txt
# Generated by version 1.03 BETA 20
index 0
# 50 MHz
    global.multiplier =   4
    global.divider    =   1
    pclk.phase   = -50
    clken.phase  =  50
    bclk.phase   = -40
    cpuclk.phase = 190
    clk90.phase  = 280
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  60
index 1
# 55 MHz
    global.multiplier =  22
    global.divider    =   5
    pclk.phase   = -50
    clken.phase  =  50
    bclk.phase   = -20
    cpuclk.phase = 220
    clk90.phase  = 310
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  20
index 2
# 60 MHz
    global.multiplier =  24
    global.divider    =   5
    pclk.phase   = -50
    clken.phase  =  50
    bclk.phase   = -20
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  60
index 3
# 65 MHz
    global.multiplier =  26
    global.divider    =   5
    pclk.phase   = -45
    clken.phase  =  45
    bclk.phase   = -50
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  60
index 4
# 70 MHz
    global.multiplier =  56
    global.divider    =  10
    pclk.phase   = -45
    clken.phase  =  45
    bclk.phase   = -40
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  60
index 5
# 75 MHz
    global.multiplier =  30
    global.divider    =   5
    pclk.phase   = -40
    clken.phase  =  40
    bclk.phase   =  50
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  16
    clken.divider  =  32
    bclk.divider   =  64
    cpuclk.divider =  64
    clk90.divider  =  64
    emu_extra_phase =  40
index 6
# 80 MHz
    global.multiplier =  28
    global.divider    =   5
    pclk.phase   = -40
    clken.phase  =  40
    bclk.phase   =  50
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  14
    clken.divider  =  28
    bclk.divider   =  56
    cpuclk.divider =  56
    clk90.divider  =  56
    emu_extra_phase =  40
index 7
# 85 MHz
    global.multiplier =  21
    global.divider    =   5
    pclk.phase   = -45
    clken.phase  =  45
    bclk.phase   =  70
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  10
    clken.divider  =  20
    bclk.divider   =  40
    cpuclk.divider =  40
    clk90.divider  =  40
    emu_extra_phase =  60
index 8
# 90 MHz
    global.multiplier =  27
    global.divider    =   5
    pclk.phase   = -45
    clken.phase  =  45
    bclk.phase   =  80
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  12
    clken.divider  =  24
    bclk.divider   =  48
    cpuclk.divider =  48
    clk90.divider  =  48
    emu_extra_phase =  60
index 9
# 95 MHz
    global.multiplier =  19
    global.divider    =   4
    pclk.phase   = -45
    clken.phase  =  45
    bclk.phase   =  90
    cpuclk.phase = 180
    clk90.phase  = 270
    pclk.divider   =  10
    clken.divider  =  20
    bclk.divider   =  40
    cpuclk.divider =  40
    clk90.divider  =  40
    emu_extra_phase =  60
index 10
# 100 MHz
    global.multiplier =  25
    global.divider    =   5
    pclk.phase   = -20
    clken.phase  =  30
    bclk.phase   =  40
    cpuclk.phase = 220
    clk90.phase  = 310
    pclk.divider   =  10
    clken.divider  =  20
    bclk.divider   =  40
    cpuclk.divider =  40
    clk90.divider  =  40
    emu_extra_phase =  0
index 11
# 105 MHz
    global.multiplier =  21
    global.divider    =   5
    pclk.phase   = -20
    clken.phase  =  40
    bclk.phase   =  60
    cpuclk.phase = 200
    clk90.phase  = 290
    pclk.divider   =   8
    clken.divider  =  16
    bclk.divider   =  32
    cpuclk.divider =  32
    clk90.divider  =  32
    emu_extra_phase =  30
index 12
# 110 MHz
    global.multiplier =  22
    global.divider    =   5
    pclk.phase   = -10
    clken.phase  =  50
    bclk.phase   =  60
    cpuclk.phase = 240
    clk90.phase  = 330
    pclk.divider   =   8
    clken.divider  =  16
    bclk.divider   =  32
    cpuclk.divider =  32
    clk90.divider  =  32
    emu_extra_phase =   0
index 13
# 115 MHz
    global.multiplier =  23
    global.divider    =   5
    pclk.phase   = -10
    clken.phase  =  50
    bclk.phase   =  60
    cpuclk.phase = 250
    clk90.phase  = 340
    pclk.divider   =   8
    clken.divider  =  16
    bclk.divider   =  32
    cpuclk.divider =  32
    clk90.divider  =  32
    emu_extra_phase =   0
index 14
# 120 MHz
    global.multiplier =  30
    global.divider    =   5
    pclk.phase   = -40
    clken.phase  =  40
    bclk.phase   =  60
    cpuclk.phase = 200
    clk90.phase  = 290
    pclk.divider   =  10
    clken.divider  =  20
    bclk.divider   =  40
    cpuclk.divider =  48
    clk90.divider  =  48
    emu_extra_phase =  60
